Wang, Runsheng

Associate Professor

Research Interests: Nanoscale CMOS devices and characterization, technology and circuit interaction (device-circuit co-design), new-paradigm computing

Office Phone:

Email: wrs@pku.edu.cn

Wang, Runsheng is an Associate Professor of Electrical Engineering (Microelectronics) in the School of EECS, Peking University. He received the B.S. and Ph.D. (highest honors) degrees from Peking University, Beijing, China, in 2005 and 2010, respectively. From November 2008 to August 2009, he was a Visiting Scholar with Purdue University, West Lafayette, IN, USA. His research interests include nanoscale CMOS devices and characterization, technology and circuit interaction (device-circuit co-design), and new-paradigm computing.

Dr. Wang has authored/coauthored 1 book, 3 book chapters, and over 100 scientific papers, including 24 papers in IEEE Electron Device Letters (EDL) or IEEE Transactions on Electron Devices (T-ED), and 30 papers in International Electron Devices Meeting (IEDM) or Symposium on VLSI Technology (VLSI-T), which are the top journals and the flagship conferences, respectively, in the IC device area. His work has been listed in International Technology Roadmap for Semiconductors (ITRS). He has been granted 12 US patents and 29 Chinese patents. He also serves on the Editorial Board of Scientific Reports, and SCIENCE CHINA: Information Sciences, and has served on the Technical Program Committee of many conferences, including IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2017, as Track co-Chair), IEEE Nanoelectronics Conference (INEC 2016, as Track Chair), IEEE International Reliability Physics Symposium (IRPS 2016), etc. Dr. Wang was awarded 2013 IEEE EDS Early Career Award, by IEEE Electron Device Society (EDS), who was the first recipient of this award from outside the USA. He also received many other awards, including NSFC Award For Excellent Young Scientists by the National Natural Science Foundation of China (NSFC), and Natural Science Award (First Prize) by the Ministry of Education (MOE) of China.

    Dr. Wang has made continuous contributions to the Silicon CMOS Technology, with specialties in multi-gate Si nanowire FET (SNWT), and in device variability and reliability. Several key technical contributions are as follows.

    (1) He experimentally demonstrated and then answered some mysteries of Si nanowire device physics. For example, he was the first to experimentally show quasi-ballistic transport in SNWTs at room temperature, which was later confirmed by Samsung. He was the first to show the non-negligible self-heating in SNWTs, which was later followed by IBM and Toshiba. He was also the first to investigate the unique reliability and low-frequency noise behaviors in SNWTs. All these work reveal clear and deep understanding of the Si nanowire device physics and thus provide helpful design guidelines for SNWTs.

   (2) He contributes deeply in the characterization and theoretical modeling of line-edge/width roughness (LER/LWR). For example, he was the first to point out the cross-correlation of LER. Based on this, he further proposed the first full-set compact model for static random variations in FinFET, including Fin-edge roughness, gate-edge roughness, as well as metal-gate granularity, which can be embedded into industry-standard BSIM-CMG model, thus is very helpful for FinFET circuit design.

(3) He was among the first to point out the stochastic NBTI effect in transistor aging. Thus, for the aging-induced dynamic variation, apart from conventional time-dependent device-to-device variation, he found that this effect induces a new source of cycle-to-cycle variation due to the random occupation of trap states in each operation cycle during circuit aging.