Micro/nanofabrication and Integration Technologies

Release time:2017-10-05

Microfabrication and integration technologies are fundamental supporting technologies to the novel micro/nanoscale electronic device and the micro/nano-electro-mechanical system (M/NEMS), which drive the development of microelectronics and M/NEMS. In the past several years, we focused on the silicon-based micro/nanofabrication and integration technologies and explored new processes for a variety of functional materials, from Parylene (polymer) to Ti, Mo and W (metals).

The main contributions are included as follows:

1) Micro/nanofabrication and integration for advance microelectronics devices.

Aiming at the continuous scaling of CMOS technology, we proposed several novel process methods for fabricating nano-scale CMOS devices including silicon nanowire transistors, FinFET and high-mobility channel transistors. The major achievements include controllable nanowire formation by self-limiting process, self-saturated ultra-thin silicide formation using barrier layer, GIDL characterization and modeling in silicon nanowire transistors, novel silicon nanowire transistors for ESD application, TCAD optimization for FinFET and so on. Meanwhile, several Ge-based microfabrication techniques have been developed, including solid-phase epitaxial regrowth for highly activating n-type dopant in Ge device, plasma emersion technology for interface treatment in Ge device, post-germanide dopant segregation technique for contact barrier modulation, multi-implant-multi-anneal technique for improving n-type dopant activation, plasma treatment and co-implantation for highly thermal stable germanide and so on. Monolithic 3D IC integration was also studied, including low-cost high-efficient thin film process with strained capping layer and boundary limitation, vertical nanowire architecture design and process integration, core-shell nanowire transistor design and so on.

2) Micro/nanofabrications for M/NEMS.

The world-class manufacturing process for nano-scale high-aspect-ratio structure of monocrystalline silicon has been successfully developed, using which monocrystalline silicon nanometer barrel array has been realized, whose wall thickness is 6.7 nm and aspect-ratio is more than 50:1. Facing the 7 nm oriented process node, the fundamental processing capacity has been equipped for the next generation of nano-scale IC research. Another representative work is that three sets of MEMS standard process have been developed, which have provided hundreds of MEMS chip research projects with fabrication technology service and directly supported domestic top-level micro gyroscope and accelerometer manufacturing. In addition, according to the systematical research on process-related bulk silicon mechanical characteristics extraction method of MEMS microstructures, a series of microstructure parameter extraction and process quality control methods have been utilized in MEMS production line.

3) Integration technology.

To improve function density of integration, through-silicon-via (TSV) based 3D integration has been introduced and shown promising progresses recent year, including design and simulation of 3D module, process development and packaging/testing of multi-layer chip/wafer, such as 10 layer SRAM stacking prototype. 3D-TSV Package makes chip-level heterogeneous integration possible while satisfies the demands for high performance, small footprint and high reliability in aerospace applications. The research focuses on the reliability of TSV in aerospace applications, thermal management for 3D microsystems, key fabrication technologies for silicon interposer and high reliable TSV redundancy architecture.

4) Multi-material microfabrication technologies.

Diversiform novel micro/Nano fabrication technologies have been proposed, including the focused-ion-beam stress and material-redistribution induced three-dimensional (3D) deformations, the oxygen plasma stripping of polymers for Nano-forests synthesis, the crossed spacer and overlapped spacer techniques, diffraction-introduced photolithography and etc. These technologies have been applied to produce various Micro/Nano functional structures in electronic, optical and sensing devices. Meanwhile, a highly reliable and controllable ultra-thin Parylene deposition approach for the deposition with thickness as small as 1 nm has been developed. An annealing process for the autofluorescence enhancement of Parylene C has been advanced. This technique has been implemented for various fluorescence marking applications including addressable neuronal electrophysiology. The Parylene C caulked PDMS process to enabling a hybrid material (pcPDMS) with a low small molecule permeability has been optimized. Besides, several metal-based deep etching process as a reliable three-dimensional microfabrication technology has been proposed. ICP etching of bulk metal material combined with other microfabrication technologies offers numerous opportunities in MEMS applications.

The microfabrication platform served for hundreds of MEMS research institutions all over the country. The standard process and platform for the micro-electro-mechanical system (M/NEMS) won the second prize of National Technology Invention Award (2006).

Besides the academic achievements, the key technologies realized the industry transformation, which gives strong supports to the development of IC and MEMS in China. Based on the rich experiences in MEMS research, especially in the standardized MEMS fabrication techniques proposed in 2016 and the first IEC MEMS standard (IEC 62047-25, Silicon based MEMS fabrication technology-measurement method of pull-press and shearing strength of micro bonding area) from the mainland China, two other IEC MEMS standards were proposed to IEC standard committee presently and are under review now (in the CD stage). We have close relationships with Intel, Samsung, SIMTech, HuaWei, SMIC, ASTRI, CETC, etc., which facilitate the development our microfabrication and integration technologies.